Why doesn't my Intel® Arria® 10 SoC boot using FPGA boot mode when all dedicated I/O are unused? - Why doesn't my Intel® Arria® 10 SoC boot using FPGA boot mode when all dedicated I/O are unused? Description Due to a problem in Intel® Quartus® Prime Pro/Standard Software, OSC_CLK_1_HPS, nPOR_RST and nRST_HPS input ports are disabled by U-boot settings. Resolution 1) Move to the hps_isw_handoff folder in your design. 2) Open hps.xml 3) Find the following section. <csr>  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_drv_strg' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_drv_strg' value='0' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_drv_strg' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_drv_strg' value='0' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.input_buf_en' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_drv_strg' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_drv_strg' value='0' /> 4) Replace above 3 unused settings with the following OSC_CLK_1_HPS, nPOR_HPS and nRST_HPS settings, and save hps.xml. <csr>  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.input_buf_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_drv_strg' value='10' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.input_buf_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_drv_strg' value='10' />  <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.rtrim' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.input_buf_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.wk_pu_en' value='1' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_slw_rt' value='0' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_drv_strg' value='8' /> <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_drv_strg' value='10' /> 5) Create one uboot project and make the bin file based on new handoff file Custom Fields values: ['novalue'] Troubleshooting 2205688804 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1 ['Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']