Why is the PCI Express endpoint stuck in DETECT.QUIET when using the example Avalon-MM Qsys design? - Why is the PCI Express endpoint stuck in DETECT.QUIET when using the example Avalon-MM Qsys design? Description The Avalon®-MM Stratix® V Hard IP for PCI® Express example design, which is available from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ directory, will not successfully link train in hardware or when using serial mode in simulation. This is because the endpoint is held in reset. Resolution To workaround this problem, open the design in Qsys, and remove the connection from the nreset_status output from the DUT module to the mgmt_rst_reset input on the alt_xcvr_reconfig_0 module. This problem has been fixed starting in version 13.1 of the Quartus® II Software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0.1 ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']