Why does the Intel® Stratix® 10 H-Tile Avalon® Streaming (Avalon-ST) for PCI Express* with multiple PFs enabled fail to boot? - Why does the Intel® Stratix® 10 H-Tile Avalon® Streaming (Avalon-ST) for PCI Express* with multiple PFs enabled fail to boot? Description The Intel® Stratix® 10 H-Tile Avalon® Streaming (Avalon-ST) for PCI Express* Hard IP supports 4 Physical Functions (PF0-PF3). Each PF can have an expansion ROM BAR enabled. Due to a bug in the PCIe* Hard IP RTL, the Expansion ROM BARs for PF2/PF3 are always enabled, and their size is fixed to 64KB. This bug may cause systems to fail to boot up. Resolution Intel® has implemented a soft IP fix in the Intel® Quartus® Prime Pro version 19.1 software that responds with 0x0000 to any memory reads initiated by the host targeting the expansion ROMs attached to PF2/PF3. Custom Fields values: ['novalue'] Troubleshooting 2007758345 True ['Avalon-ST Stratix® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']