Why does the example design testbench for the single channel E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GBASE-KR variant not complete in either Ncsim® or Xcellium®? - Why does the example design testbench for the single channel E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GBASE-KR variant not complete in either Ncsim® or Xcellium®? Description Due to a problem in the Intel® Quartus® Prime Pro software version 19.4, the example design testbench for E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP variant with a single channel of 10GBASE-KR selected will not complete when using Ncsim® or Xcellium®. Resolution To work around this issue, increase the number of channels in your 10GBASE-KR variant to greater than ‘1’ when simulating the example design with Ncsim or Xcellium. This problem is fixed starting with the Intel® Quartus® Prime Pro software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 14010512151 False ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']