SystemVerilog for Design - 3 Days - Enroll Now This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design. The student will learn about the constructs and features in SystemVerilog designed to capture design intent. Following best design practices enables simulation tools to analyze for correct behavior, which speeds up the design process. An introduction to SystemVerilog Assertions (SVA) is also discussed. Practical lab exercises are provided to reinforce the material. Course Content: 1. Data Types • User Defined Types • Enumerations • Type Casting • Parameterized types 2. Arrays and Strings and Structures • Packed arrays • Unpacked arrays • Structures • Unions 3. Structs & Arrays • Struct • Queue • Dynamic Arrays • Associative Arrays 4. SystemVerilog Building Blocks • Reducing RTL ambiguity • always derivatives 5. RTL Programming 6. Procedural Statements • Operators 7. Control Flow Statements • Loop statements • Decision statements • case/if…else modifiers 8. Hierarchy • Ports • Implicit port connections • Functions • Tasks • Packages 9. Interfaces • Signal style • Interface as port type • Modports • BFM style 10. Assertions • SVA • Immediate assertions • Concurrent assertions 11. Concurrent assertion basics • Boolean expressions • Sequences • Properties • Verification directives 12. Sequence Blocks • Sequence operators • Sequence methods 13. Property Blocks 14. Local data variables 15. Verification directives • Bind directive 16. Clocks • Clock Syntax • Input and Output Skew • Testbench and Clocks • Clock Cycle Delays • Scheduler • Multiple Clocks 17. Targeting Altera FPGAs and SoCs • Focus on Altera specific implementation and chip-level optimization 18. Randomization • Constrained random verification • Random numbers in SystemVerilog • std::randomize • Constraint syntax • Seeding and random stability • Saving & restoring seeds • Random sequence of valid actions • Randcase • Randsequence 19. Coverage • Functional coverage • Coverage bins • Further options • Transition coverage • Cross coverage • Adjusting stimulus using coverage 20. Other Language Features Prerequisites: - Familiarity with Verilog for RTL Design Tools Required: - RTL Simulation Tools. FA_SYSTEMVERILOG.