Why does the Deinterlacer II IP core drop a line for every other frame in simulation? - Why does the Deinterlacer II IP core drop a line for every other frame in simulation? Description Due to a problem with Intel® Quartus® Prime software version 16.1, you may encounter the above problem in simulation if the Deinterlacer II IP core is configured with " Bob " deinterlacing algorithm and produce one frame for every F0 field . Resolution To work around this problem configure the Deinterlacer II IP to produce one frame for every F1 field . This problem has been fixed in Intel Quartus Prime software version 17.1. Custom Fields values: ['novalue'] Troubleshooting FB: 456447; False ['Deinterlacer II (4K HDR passthrough) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 16.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']