TLS-09 - High-Level Synthesis (HLS) for FPGA Acceleration - 2 Days - Enroll Now High Level Synthesis (HLS) is a transformative methodology that enables hardware designers and software engineers to describe complex algorithms in C++ and automatically compile them into synthesizable RTL code, dramatically accelerating FPGA development cycles for compute intensive applications. This course provides comprehensive training in the Altera® HLS Compiler Pro Edition and its integration with the Altera Quartus Prime design environment. Students learn HLS specific C++ language extensions, optimization directives, memory architecture strategies, and the complete design flow from algorithmic specification to a programmed FPGA target. Course Content: 1. Introduction to HLS — Motivation, History, and Scope 2. Altera HLS Compiler Architecture and Compilation Pipeline 3. HLS Component Model — Tasks, Kernels, and Interfaces 4. C++ for HLS — Supported Subset, Data Types, and Restrictions 5. Compilation, Simulation, and the HLS Analysis Report 6. Quality of Results (QoR) Metrics — Latency, II, and Resource Utilization 7. Arbitrary Precision Integer Types — ac_int and hls_uint / hls_int 8. Fixed Point Arithmetic — ac_fixed and Precision Analysis 9. HLS Specific C++ Pragmas and Attributes — Overview and Philosophy 10. Streaming Interfaces — hls::stream, Burst Reads, and FIFOs 11. Dataflow and Loop Based Pipelining — II and Throughput Concepts 12. Verification Strategies — HLS Testbenches and Co-Simulation 13. Loop Analysis — Dependency Analysis and II Bottlenecks 14. Loop Unrolling, Pipelining, and Flattening Directives 15. Loop Fusion, Fission, and Interchange Techniques 16. On-Chip Memory Architecture — Block RAM, MLABs, and Registers 17. Memory Partitioning, Banking, and Coalescing Concepts 18. Shift Register Inference and Cyclic Buffer Patterns 19. DSP Case Study — 2D Convolution Kernel Optimization 20. Interface Synthesis — Avalon-MM, Avalon-ST, AXI4, and AXI4-Stream 21. HLS Component Packaging as Altera IP (Platform Designer) 22. Platform Designer System Integration with HLS IP 23. Quartus Prime Synthesis and Fitting — Constraints for HLS Logic 24. Timing Closure Techniques for HLS Generated Datapaths 25. On-Chip Debugging — Signal Tap and the HLS Debug Environment 26. Floating Point HLS — IEEE 754 Support and Latency Implications 27. Advanced Dataflow — Task Level Parallelism and Nested Pipelines 28. HLS for AI/ML Inference — Quantization, Pruning, and Layer Mapping 29. HLS and OpenCL Interoperability on Altera FPGAs 30. Use Cases — Communications, Image Processing, and Financial Analytics 31. HLS Methodology Best Practices and Design Reuse Patterns 32. Course Review and Path to HLS Advanced Optimization Prerequisites: - Solid proficiency in C or C++ programming (functions, pointers, arrays, structs, templates) - Fundamental understanding of digital logic design (combinational and sequential circuits) - Familiarity with basic FPGA architecture concepts (LUTs, registers, block RAM, DSP blocks) - Experience using a Linux or Windows command line environment - Working knowledge of RTL design in VHDL or Verilog / SystemVerilog - Prior exposure to Altera Quartus Prime - Understanding of standard digital interfaces (AXI4, Avalon, memory mapped I/O) - Basic awareness of fixed point arithmetic and precision tradeoffs - Completion of FPGA Authority "Introduction to FPGA Design" or equivalent experience Tools Required: - Altera HLS Compiler Pro Edition - Altera Quartus Prime Pro Edition - Altera ModelSim / Questa - Altera Platform Designer - Altera FPGA SDK for OpenCL - GCC / G++ Toolchain - Microsoft Visual Studio - Python Course Code: TLS-09. FA_HLS.