High-Level Synthesis (HLS) for FPGA Acceleration - 3 Days - Enroll Now High-Level Synthesis (HLS) enables C++ algorithmic descriptions to be automatically compiled into synthesizable RTL code, dramatically accelerating FPGA development time for compute-intensive applications. This course provides comprehensive training in the Intel HLS Compiler, covering HLS-specific C++ language extensions, optimization directives, memory architecture, and the integration of HLS-generated components into Quartus Prime designs. Use cases are also explored. Course Content: 1. High Level Synthesis Concepts & HLS Compiler Introduction 2. The HLS Programming Model 3. Controlling Hardware Architecture with HLS Optimizations 4. HLS Interfaces 5. Loops and Conditional Statements 6. Loop Optimizations 7. HLS Data Types 8. Data Type Optimizations 9. Memory Architecture Optimization 10. HLS Verification & Performance Analysis 11. HLS Integration and Optimization Example Prerequisites: - Basic understanding of the C++ programming language - Basic understanding of FPGAs and the Altera® Quartus Prime Software Tools Required: - Altera® Quartus Prime Software. FA_HLS.