Why does the PCIe core return Unsupported Request for Type0 Configuration Read request? - Why does the PCIe core return Unsupported Request for Type0 Configuration Read request? Description When the PCIe® core is configured as End Point (EP), its Completer ID in configuration space is assigned by the type0 Configuration Write request (CfgWr0). Subsequent type0 Configuration Read requests (CfgRd0) must use this Completer ID in the third dword of TLP header format. If the host sends CfgRd0 request with Completion ID different from the value given by the previous CfgWr0, the core will respond with Unsupported Request Completion message. To fix this problem, please make sure that the Completer ID in CfgRD0 request must be the same as the value assigned by its previous CfgWr0. Related Articles Why does the PCIe core send Unsupported Request completion message to my first good MRD request? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']