Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer? - Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer? Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some. Custom Fields values: How To QS-194983 novalue No plan to fix 26.1 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs']