Why do I see warnings when using the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and LVDS I/O, or 1000BASE-X/SGMII PCS and LVDS I/O is selected in the Agilex™ 7 FPGA Triple-Speed Ethernet IP? - Why do I see warnings when using the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and LVDS I/O, or 1000BASE-X/SGMII PCS and LVDS I/O is selected in the Agilex™ 7 FPGA Triple-Speed Ethernet IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.4, the warnings shown will be seen when selecting the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS, and LVDS I/O or the 1000BASE-X/SGMII PCS and LVDS I/O option is selected in the Agilex™ 7 FPGA Triple-Speed Ethernet IP core. Warning: test.eth_tse_0.i_lvdsio_terminator_0.pll_areset_iopll: Associated reset sinks not declared Warning: test.eth_tse_0.iopll: Able to implement PLL - Actual VCO frequency differs from requested setting Warning: test.eth_tse_0.ref_clk_module.out_clk/iopll.refclk: iopll.refclk requires 125000000Hz, but source has frequency of 0Hz Resolution These warnings can be safely ignored as functionality is not impacted when using the Agilex™ 7 FPGA Triple-Speed Ethernet IP core. Custom Fields values: ['novalue'] Troubleshooting 1507651024 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']