Question related to clock resource on Stratix V GX evaluation board - Question related to clock resource on Stratix V GX evaluation board Hi, I have difficulty finding the clock resource on Intel Stratix V GX edition transceiver signal integrity development kit. I have read the reference manual to this evaluation board, I saw there are 4 oscillators at 625MHz, 644.53125 MHz, 706.25 MHz, and 875 MHz available on board, but the device pin number is not available in the manual. I am wondering if it is possible to utilize these oscillators for clock purpose for my verilog code? I am using clock control block (ALTCLKCTRL) IP core. Please guide me how I should proceed. Thank you, Steven Replies: Re: Question related to clock resource on Stratix V GX evaluation board I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com/s/?language=en_US ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: Question related to clock resource on Stratix V GX evaluation board Hi Kenny_Tan, Thank you for your reply. That would be all questions I have for now. Best Regards, Replies: Re: Question related to clock resource on Stratix V GX evaluation board Do you have further question? Replies: Re: Question related to clock resource on Stratix V GX evaluation board The high-speed clocks on the Stratix V GX Signal Integrity Kit—those running at 625 MHz, 644.53125 MHz..... —are tied strictly to the transceiver circuits. They aren’t usable for core logic, can’t feed the main PLLs, and won’t connect through something like ALTCLKCTRL. They’re simply not wired for general use in your design. If you need a clock for your logic, you’ll have to look elsewhere—like a lower-frequency on-board oscillator (often something like 50 MHz), or bring in your own via an HSMC port or SMA connector. Just make sure the pin you use can actually connect to the FPGA’s internal clock routing. Replies: Re: Question related to clock resource on Stratix V GX evaluation board Connection of oscillators is shown in reference manual, figure 2-6. Replies: Re: Question related to clock resource on Stratix V GX evaluation board Thank you sstrell, I'll look into the schematics of the kit. Replies: Re: Question related to clock resource on Stratix V GX evaluation board Hi FvM, Thank you for your reply. Can you please let me know which page in the manual this information is mentioned? Thank you. Replies: Re: Question related to clock resource on Stratix V GX evaluation board According to reference manual, said clocks are connected exclusively as transceiver reference clocks, thus not available to feed core clock network and PLLs. Replies: Re: Question related to clock resource on Stratix V GX evaluation board Have you downloaded the full kit installation? https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/v-gx-signal-integrity.html The schematics would have all the detail you need.