VCS-MX Simulation with Simulation Script vcsmx_setup.sh Fails at 0ns - VCS-MX Simulation with Simulation Script vcsmx_setup.sh Fails at 0ns Description A VCS-MX simulation of a UniPHY-based external memory interface IP core in VHDL with the provided simulation script vcsmx_setup.sh fails at time 0ns with the following error: 0 ns: ERROR: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/F_valid is 'x'. at time 0 Scope: \DUT_EXAMPLE_SIM.E0.IF0.S0.CPU_INST .the_altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench File: ./../..//submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v Line: 498. This issue affects DDR2 and DDR3 protocols, and QDR II/II and RLDRAM II when using the Nios II-based sequencer. Resolution The workaround for this issue is as follows: In a text editor, open one of the following files, whichever applies: < variant_name > _example_design/simulation/vhdl/submodules/dut_example_sim_e0_if0_s0_rst_controller.vho < variant_name > _sim/submodules/dut_e0_if0_s0_rst_controller.vho Change the initial value of the registers in the reset synchronizer from: SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q : STD_LOGIC := \'0\';� SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q : STD_LOGIC := \'0\';� SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q : STD_LOGIC := \'0\'; to: SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_0_46q : STD_LOGIC := \'1\';� SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_1_45q : STD_LOGIC := \'1\';� SIGNAL dut_example_sim_e0_if0_s0_rst_controller_altera_reset_controller_rst_controller_altera_reset_synchronizer_alt_rst_sync_uq1_altera_reset_synchronizer_int_chain_out_47q : STD_LOGIC := \'1\'; (The exact names of your signals may differ from those above, but they will contain the substring altera_reset_synchronizer_int_chain .) Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']