ALTERA QUARTUS II - ALTERA QUARTUS II Hai, ** Error: C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/INTEG NODE TOP MODULE 6JAN2021/INTEG_TOP_MODULE.vhd(234): Signal 'wrfull_sig' must have only one source since it is connected to buffer port 'wrfull_sig'. I am doing code in VHDL. I am using more than one VHDL file and added it to the main project folder. I am using this wrfull_sig in 3 of the individual projects and used this signal in my main project. I have assigned wrfull_sig as a buffer in all these 3 projects. Now, this showing this error. Can you please find a way to resolve this problem Please give a way to resolve this problem Replies: Re: ALTERA QUARTUS II Hi, We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you Best regards, KhaiY Replies: Re: ALTERA QUARTUS II Hi, Could you share the design QAR for investigation? Thanks Best regards, KhaiY Replies: Re: ALTERA QUARTUS II HAI, I am using QUARTUS PRIME LITE EDITION-18.1 VERSION Replies: Re: ALTERA QUARTUS II Hi, May I know what is the software edition (Pro/Standard/Lite) and version you are using? Kindly try to run the compilation using the latest version of the Intel Quartus Prime software. If the problem persists, you may share the design QAR file for investigation. To generate the design QAR file, click on Project > Archive Project > Archive. Thanks Best regards, KhaiY