High Bandwidth Memory in Altera FPGAs (Part 3): Implementation - 55 Minutes This is part 3 of 3. High Bandwidth Memory, or HBM2/HBM2E, is the next generation of high-speed memory built into Altera® Agilex™ 7 M-Series FPGAs and Altera® Stratix® 10 MX and DX FPGAs using System in Package (SiP) technology. HBM2/HBM2E enables the highest levels of bandwidth not feasible with other solutions. Multiple DRAM layers are connected to a base I/O layer to form a 3-D, high-speed memory connected to and controlled directly by dedicated hard memory controllers. Integrating HBM directly in the FPGA package reduces board size and cost, simplifies and reduces power requirements, and makes it easy to add to your Altera® Quartus® Prime Pro Edition project. This final part discusses how to implement the HBM2 or HBM2E in a design, as well as how to simulate functionality and measure the efficiency and performance of the interface. Course Objectives At course completion, you will be able to: Understand the benefits of using the High Bandwidth Memory (HBM) integrated into supported devices Know about the features of and options for the hardened HBM controller Create an implementation of the HBM interface and controller in the Altera® Quartus® Prime Pro edition software Skills Required Basic knowledge of the Altera® Quartus® Prime software Familiarity with external memory and related interfaces Familiarity with the Arm AMBA 4 AXI interface standard If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHBMIMPL. FPGA_OHBMIMPL. <p>High Bandwidth Memory in Altera FPGAs (Part 3): Implementation</p>