Are there any differences in behavior between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method of Stratix® V devices? - Are there any differences in behavior between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method of Stratix® V devices? Description Yes, you may see differences in behavior between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method in Stratix® V devices. Resolution For RTL simulation, you may write the difference in the MIF file using the direct write method. For hardware, the entire Rx CDR PLL MIF file must be written. Custom Fields values: ['novalue'] Troubleshooting 1408190410 False ['PLL IP'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1 ['Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']