Why does the 10G Multi-IP configured design, including the F-tile Ethernet Intel® FPGA IP, fail at “Support Logic Generation” when implementing multiple instances? - Why does the 10G Multi-IP configured design, including the F-tile Ethernet Intel® FPGA IP, fail at “Support Logic Generation” when implementing multiple instances? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, you might see a “Support Logic Generation” failure with your design, including the F-tile Ethernet Intel® FPGA IP configured, fail at “Support Logic Generation” when implementing multiple instances. Resolution There is no workaround available. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16019995864 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']