How are the IO pins that migrate to NC configured by the Quartus II software, when compiling a design targeting Arria V, Cyclone V or Stratix V devices, with migration devices selected? - How are the IO pins that migrate to NC configured by the Quartus II software, when compiling a design targeting Arria V, Cyclone V or Stratix V devices, with migration devices selected? Description When compiling a design targeting Arria® V, Cyclone® V or Stratix® V devices, with migration devices selected, IO pins that migrate to NC will be configured as per the project's device-wide Unused Pin settings in the Quartus® II software. By default this is set to "As input tri-stated with weak pull-up". Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']