DDR2 Interfaces on Cyclone V SoC Devices May Fail Read Capture Timing - DDR2 Interfaces on Cyclone V SoC Devices May Fail Read Capture Timing
Description This problem affects DDR2 products. DDR2 interfaces on Cyclone V SoC devices may fail Read Capture Timing in Report DDR . Resolution The workaround for this issue is to choose a faster speed grade DDR2 device. This issue will be fixed in a future version.
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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13.0.1
['Cyclone® V FPGAs and SoCs']
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['novalue'] - 2021-08-25
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