Why the ECC error flag incorrectly asserted in the Triple-Speed Ethernet Intel® FPGA IP? - Why the ECC error flag incorrectly asserted in the Triple-Speed Ethernet Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Software version 18.1 and earlier, the mac_eccstatus signal of the the Triple-Speed Ethernet Intel® FPGA IP core incorrectly flags both correctable and uncorrectable errors when the ECC protection feature is enabled. Resolution No work around to this problem exists. This problem has been fixed in the Intel® Quartus® Prime Software version 19.1 or later. Custom Fields values: ['novalue'] Troubleshooting 1506968625 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 19.1 17.1 ['Arria® V GZ FPGA', 'Arria® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']