Why is the efficiency of the Cyclone® V and Arria® V hard memory controller lower than expected for single port designs? - Why is the efficiency of the Cyclone® V and Arria® V hard memory controller lower than expected for single port designs? Description The Multi-Port Front End (MPFE), used with the Hard Memory Controller for Arria® V and Cyclone® V devices, contains an arbiter that enables load balancing across multiple ports. In addition, the MPFE will always grant access to a different port after it has finished serving a port. This behavior means that where the MPFE only receives traffic on one port, either because no other ports have pending transactions or because a single port variation is generated, the controller will implement writes in 5 clock cycles instead of 4 clock cycles. Reads are not affected. This behavior may also be seen in multi-port MPFE configurations. Resolution There is no workaround for this behavior. Custom Fields values: ['novalue'] Troubleshooting 1408175536 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 11.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']