Why doesn’t the tx_pma_elecidle signal on the Intel® Arria® 10 or Cyclone® 10 GX device Native PHY IP put the transceiver TX pins in a tristate or high-impedance mode? - Why doesn’t the tx_pma_elecidle signal on the Intel® Arria® 10 or Cyclone® 10 GX device Native PHY IP put the transceiver TX pins in a tristate or high-impedance mode? Description Asserting the tx_pma_elecidle signal on the Intel® Arria® 10 or Intel® Cyclone® GX device, Native PHY IP does not tristate or put the transceiver TX pins in a high-impedance mode. Asserting the tx_pma_elecidle signal on the Intel® Arria® 10 or Intel® Cyclone® GX device, Native PHY IP stops data transmission and causes the output signal to exhibit the Transmitter Vocm on both P and N pins of the differential pair. The TX termination remains connected to the Vcm generator when the tx_pma_elecidle signal is asserted. Resolution This information may be added to a future version of the Intel® Arria® 10 Transceiver PHY User Guide and Intel® Cyclone® 10 GX Transceiver User Guide. Custom Fields values: ['novalue'] Troubleshooting 1808295443 False ['Transceiver Native PHY Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']