Entity "cpriphy_ftile_wrapper" instantiates undefined entity "ex_24G_simple_model". This may cause the generated IP information to be incomplete. - Entity "cpriphy_ftile_wrapper" instantiates undefined entity "ex_24G_simple_model". This may cause the generated IP information to be incomplete. Description The simplified IP core model in simulation (Support 24G non-FEC only) option supports: System PLL frequency: 805.664062 MHz Enable CDR clock output not selected PMA reference frequency: 184.32MHz Select design: Single instance of IP core Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, other configurations than the listed when the simplified IP core model in simulation (Support 24G non-FEC only) option is selected will pass IP example design generation without errors, however the Quartus® compilation will fail with errors pointing to the illegal configuration of the listed items. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 15015533142 False ['F-Tile CPRI PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']