How can I make the HPS SPI Master SS signal stay low for the whole transaction period? - How can I make the HPS SPI Master SS signal stay low for the whole transaction period? Description Some SPI Slaves may require the SPI Master to hold the SS line low during the whole SPI transaction period. The HPS SPI Master can be configured to function in that manner with workaround below. Resolution With reference to HPS address map in http://www.altera.com/literature/hb/cyclone-v/hps.html , set spim0->ctrlr0->scph [bit 6] to 1. Custom Fields values: ['novalue'] Troubleshooting 0 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 5.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']