Why does the CPRI v6.0 Intel® FPGA IP generate multiple start-of-packet words on the GMII RX Output? - Why does the CPRI v6.0 Intel® FPGA IP generate multiple start-of-packet words on the GMII RX Output? Description Due to a problem with the CPRI v6.0 Intel® FPGA IP core in the Intel® Quartus® Prime software v17.1, you may observe multiple initial start-of-packet on the GMII RX output if there are idle cycles in the gmii_rxdv within a packet. Resolution No workaround for this problem exists. This problem has been fixed in Intel® Quartus® Prime Edition software version 19.1. Custom Fields values: ['novalue'] Troubleshooting 2205697652 False ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 17.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']