Error nofile(37) in protected region - Error nofile(37) in protected region Description You may experience the above error while simulating a VHDL-based DDR3 UniPHY memory controller design with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If an error occurs in the encrypted fileset, a cryptic message like the one above will be generated. Resolution Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file located in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above error. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']