Why doesn't the CDR freeze feature work well when more than one channel of F-Tile PMA/FEC Direct PHY FPGA IP are used ? - Why doesn't the CDR freeze feature work well when more than one channel of F-Tile PMA/FEC Direct PHY FPGA IP are used ? Description Due to a problem in the F-Tile PMA/FEC Direct PHY Intel FPGA IP in the Quartus® Prime Pro Edition Software version 23.4 and earlier, the CDR is not frozen when assert fgt_rx_cdr_freeze signal when using more than 1 channel in one F-Tile. Resolution This feature is scheduled to be supported in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15015760584 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']