Do differential SSTL and HSTL inputs in Cyclone® III and Cyclone® IV device series require a VREF input to reference? - Do differential SSTL and HSTL inputs in Cyclone® III and Cyclone® IV device series require a VREF input to reference? Description Yes, usage of these I/O standards as inputs does also require a VREF input. This is because in Cyclone® III and Cyclone® IV device series, these differential inputs are treated as two single-ended HSTL and SSTL inputs and only one of them is decoded. Hence a VREF is required to define the signal state. Resolution N/A Related Articles Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices? Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']