Why do the out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP fail to toggle when simulating the Intel Agilex® 7 F-Tile FPGA PHY IPs? - Why do the out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP fail to toggle when simulating the Intel Agilex® 7 F-Tile FPGA PHY IPs? Description The o ut_refclk_fg t and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP will not toggle in the simulation waveform. However, Intel Agilex® 7 F-Tile FPGA PHY IPs are still functional in simulation. Resolution There is currently no plan to fix this problem. Custom Fields values: ['novalue'] Troubleshooting 14013803340 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']