This error will occur if you have multiple host (host for sharing PLL/DLL) external memory interface controller cores being fed by only one clock input pin in Stratix® V devices. - This error will occur if you have multiple host (host for sharing PLL/DLL) external memory interface controller cores being fed by only one clock input pin in Stratix® V devices. Description This error will occur if you have multiple host (host for sharing PLL/DLL) external memory interface controller cores being fed by only one clock input pin in Stratix® V devices. Each host interface has to be driven by its own separate PLL, because each PLL can only drive one PHY clock tree. If you try to feed all the interface' PLLs through one clock input, the Fitter will try to use one PLL only and give the error specified above. Error messsage: Error: Could not place PHY_CLKBUF {instance_name}:{instance_name}_inst|{instance_name}_0002: {instance_name}_inst|{instance_name}_p0:p0|{instance_name}_p0_controller_phy:controller_phy_inst|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphyError: PHY_CLKBUF location is occupied Resolution To avoid this error, make sure you give a separate input clock to each host interface so the fitter uses separate PLL for each host interface and not try to use just one PLL for all the host controllers. Custom Fields values: ['novalue'] Troubleshooting 2205715554 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']