When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does changing the value of the rx_transfer_control register disable the datapath instantly and not at the packet boundary? - When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does changing the value of the rx_transfer_control register disable the datapath instantly and not at the packet boundary? Description Due to a problem with the Intel® Quartus® Prime Pro software version 19.2 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP with 1G or 2.5G speed, the RX path is enable or disabled immediately as the change of value in rx_transfer_control register. The following are the affected speed parameters: 1. 1G/2.5G 2. 1G/2.5G/10G Resolution This problem has been fixed starting in the Intel® Quartus® Prime Pro software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507296157 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']