Why does my timing degrade after implementing Distributed Sector Level based clock gating? - Why does my timing degrade after implementing Distributed Sector Level based clock gating? Description Distributed Sector Level based clock gating in Intel® Stratix® 10 or Intel Agilex® 7 devices results in a Hyper-Retiming restriction for any paths crossing from one clock sector into another, which can result in performance degradation. Distributed Sector Level-based clock gating is therefore not recommended for high-frequency clock domains or for large designs, which are implemented across multiple clock sectors and rely on Hyper-Retiming. Resolution This Hyper-Retiming restriction is scheduled to be removed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18017074307 False ['Clock Control Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']