Problem FSM - Problem FSM There is a problem that when I tried to design a FSM, the code never enters to that part. I simulated the same code in ModelSim and it was working fine. FSM_I2C : process(current_state,next_state,i2c_start,Flag,i2c_clk_previous_internal, id2c_scl_i_clock,i2c_sda_oe) begin --if (RISING_EDGE(Clk)) then case current_state is when IDLE => counter_variable <= 7; if i2c_start = '1' then next_state <= START; i2c_sda_oe <= '1'; else next_state <= IDLE; end if; when START => if Flag = '1' then i2c_sda_wr <= '0'; next_state <= ADDRESS; end if; when ADDRESS => if counter_variable /= 0 then if id2c_scl_i_clock = '1' and i2c_clk_previous_internal = '0' then counter_variable <= counter_variable - 1; i2c_sda_wr <= I2C_ADDRESS_SENSOR(counter_variable-1); end if; else if id2c_scl_i_clock = '1' and i2c_clk_previous_internal = '0' then i2c_sda_wr <= I2C_WRITE_RW; counter_variable <= 7; next_state <= ACK; end if; end if; when ACK => i2c_sda_oe <= '0'; if i2c_clk_previous_internal = '0' and id2c_scl_i_clock = '1' then next_state <= IDLE; end if; when others => next_state <= IDLE; end case; --end if; end process FSM_I2C; this is just a part of the I2C algorithm. In this case, I'm just implementing sending the address to see if my code is working fine. However, this is the output Only works when I put inside the FSM a conditional IF(RISING_EDGE(CLK)), but I don't understand why since I'm updating all the variables in other process. process (Clk,reset_reset_n) begin if reset_reset_n = '0' then current_state <= IDLE; id2c_serial_scl <= '0'; id2c_serial_sda <= '0'; elsif (RISING_EDGE(Clk)) then current_state <= next_state; id2c_serial_scl <= i2c_clk_previous_internal; id2c_serial_sda <= id2c_serial_sda_o_internal; id2c_scl_i_clock <= i2c_clk_previous_internal; end if; end process; Replies: Re: Problem FSM The problem was not the triggered in the FSM. When you have a FSM and some signals are going to change in some cases, you need to initialize them at the beginning so the FSM can see signals change in every case possible. Replies: Re: Problem FSM Hi, Let me know if any further update or concern? Thanks, Best regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer. Replies: Re: Problem FSM Hi, By using the comparison trigger condition, i'm getting the signal tap waveform below (image): May check out this video https://www.youtube.com/watch?v=WJFKBWCnAB4&t=1026s for the trigger condition details. I had sent the project file to your email. For those red coloured signals are not in the node list due to being optimized away. But can try to preserve those signals by using keep or preserve attribute check this link https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/signal-preservation.html . However, I try with keep attribute on next_state signal but that affected the waveform result. Thanks, Best regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer. Replies: Re: Problem FSM I forwarded you the project to your email Replies: Re: Problem FSM Hi, Could you provide a sample project for testing out. Can also provide personally to my email qi.sheng.ng@intel.com Thanks, Regards, Sheng