Does the Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP support changing the BAR size at run-time before enumeration? - Does the Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP support changing the BAR size at run-time before enumeration? Description The Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP do not support changing the BAR size at run-time before enumeration. The BAR Size Mask can only be set during IP GUI configuration and HDL generation. Resolution Not applicable. Custom Fields values: ['novalue'] Troubleshooting 1707015093 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']