Why does a dynamic reconfiguration operation fail when using Intel® Stratix 10 fPLL FPGA IP configured in Core mode? - Why does a dynamic reconfiguration operation fail when using Intel® Stratix 10 fPLL FPGA IP configured in Core mode? Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, when targetting an Intel Stratix® 10 L-tile or H-tile FPGA device you will see the Dynamic Reconfiguration tab in the IP editor when configuring the Intel Stratix 10 fPLL FPGA IP in Core mode. However, the dynamic reconfiguration feature is not supported for the Intel Stratix 10 fPLL FPGA IP when configured in Core mode. Resolution To work around this problem, if the dynamic reconfiguration feature is required by your design do not configure the Intel® Stratix® 10 fPLL FPGA IP in Core mode if applicable. Custom Fields values: ['novalue'] Troubleshooting 1409937065 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']