Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* 4.0x4 Root Port design example reports an error during compilation? - Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* 4.0x4 Root Port design example reports an error during compilation? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1 or earlier, the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* 4.0x4 Root Port design example reports an error during compilation. Error(21410): Verilog HDL error at s10_rp_avmm_master_hwtcl.v(130): event control statement inside subprogram is not supported for synthesis Resolution To work around this, it is necessary to generate the simulation and synthesis file separately and re-compile the design example. This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 1507965203 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 20.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']