Why does my Stratix IV scfifo and dcfifo output register get cleared during the assertion of sclr during functional simulation? - Why does my Stratix IV scfifo and dcfifo output register get cleared during the assertion of sclr during functional simulation? Description Due to a problem in the Stratix® IV scfifo and dcfifo simulation model the output register will be incorrectly cleared during the assertion of the sclr input. Resolution In hardware and gate level simulation the output register will retain its previous value. This problem is scheduled to be fixed in a future release of the Quartus Prime Standard Edition software. Custom Fields values: ['novalue'] Troubleshooting FB: 471968; False ['FIFO IP', 'Simulation', 'Debug and Verification'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue novalue ['Stratix® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']