How to set HPS SDRAM PLL reference clock resource for Cyclone® V SoC device? - How to set HPS SDRAM PLL reference clock resource for Cyclone® V SoC device? Description In Cyclone® V SoC device, there are three clock sources for hard processor system (HPS) SDRAM phase-locked loop (PLL) named eosc1_clk , eosc2_clk and f2s_sdram_ref_clk , but it's not available to specify the clock source in HPS intellectual property (IP) GUI. Resolution The selection of clock source for HPS SDRAM PLL is controlled by Preloader software: 1. Generate spl_bsp from handoff files, and pll_config.h is generated in the "generated" folder of BSP target directory. 2. In the pll_config.h file, change the following value to the expected clock resource: #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) The value 0 means to use eosc1_clk as SDRAM PLL reference clock source, 1 means to use eosc2_clk and 2 means to use f2s_sdram_ref_clk . 3. Compile the Preloader and build the Preloader image. Custom Fields values: ['novalue'] Troubleshooting NA False ['Arria® V Cyclone® V Hard Processor System IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.0 ['Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['Embedded Dev Tools SoC Suite'] ['novalue'] ['novalue']