Why does my VHDL code using the absolute function (abs) not perform correctly in the MAX PLUS® II software? (Synplicity Synplify version 5.1) - Why does my VHDL code using the absolute function (abs) not perform correctly in the MAX PLUS® II software? (Synplicity Synplify version 5.1) Description There is a synthesis error in the Syplify software version 5.1 when using the absolute function ( abs ) in your VHDL design file(s). Some incorrect values are given when negative values are passed through this function. This problem has been corrected in the Synplify software versions 5.1.5a, 5.2.1, and later, which can be downloaded from the Synplicity web site . Synplify recommends that you read the Release Notes before installing version 5.1.5a of the Synplify software. The Synplify software version 5.2.1 includes version 5.1.5a featuers as well as support for the APEX ™ 20K device family. Custom Fields values: ['novalue'] Troubleshooting 0 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 5.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']