Meeting timing for Stratix IV devices with the 100GbE MAC and PHY IP Core - Meeting timing for Stratix IV devices with the 100GbE MAC and PHY IP Core Description Cannot meet timing for Stratix IV devices with the 100GbE MAC and PHY IP Core. Resolution This issue is fixed in the 12.1 Quartus software release of the IP core. For the 12.0 release of the IP core, to improve timing margins for Stratix IV designs you may be required to over-constrain the MAC clocks. Refer to the assignments in the alt_eth_100g wrappers projects .sdc files. For example, the alt_e100_siv.sdc assignment is: if { $::TimeQuestInfo(nameofexecutable) == "quartus_fit"} { create_clock -name {clk_din} -period "360.00 MHz" [get_ports {clk_din}] create_clock -name {clk_dout} -period "360.00 MHz" [get_ports {clk_dout}] } else { create_clock -name {clk_din} -period "315.00 MHz" [get_ports {clk_din}] create_clock -name {clk_dout} -period "315.00 MHz" [get_ports {clk_dout}] } This assignment forces the fitter to attempt to push for 360 MHz, while the static timing analysis will check against 315 MHz for the MAC clocks. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Stratix® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']