Why does the Timing Analyzer report minimum period timing violation in the Intel® Arria® 10 Native Fixed Point DSP IP? - Why does the Timing Analyzer report minimum period timing violation in the Intel® Arria® 10 Native Fixed Point DSP IP?
Description A minimum timing period violation may be seen if the DSP block is not fully registered. Resolution To work around this problem, enable the input, output, and pipeline register using the IP GUI to ensure timing is met when using the Intel® Arria® 10 Native Fixed Point DSP IP.
Custom Fields values:
['novalue']
Troubleshooting
1507851230
False
['Native Fixed Point DSP Arria® 10 FPGA IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
No plan to fix
18.0
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2022-02-23
external_document