Fitter fails to place PLLs and errors occur when the zero delay buffer operation mode is used for Stratix V - Fitter fails to place PLLs and errors occur when the zero delay buffer operation mode is used for Stratix V Description If you use the zero delay buffer operation mode, the Fitter can't place PLLs and generates messages similar to the following: Error: Could not place pin <pin name> . Resolution Manually place the external clock output node with a location assignment. The location depends on the PLL location and the target device. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']