Why did my DDR3 UniPHY example design fail simulation? - Why did my DDR3 UniPHY example design fail simulation? Description You may see a simulation failure when you parameterize UniPHY based DDR3 IP and simulate its auto-generated example design i f you have followed the steps below: 1) Enable 'Advanced clock phase control' in a MegaWizard PHY setting 2) Set a value other than zero in 'Additional CK/CK# phase' 3) Disable 'Advanced clock phase control' 4) Generate the IP and example design Resolution \'Advanced clock phase control\' is not used for simulation but it is used to compensate for different board skews. You need to clear the value to zero and then regenerate your IP and the example design. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']