Cyclone® V SoC Pin-Out Table: Known Issues - Cyclone® V SoC Pin-Out Table: Known Issues Description Issue 95669: In the Cyclone® V SoC (SE, ST, and SX) pin-out files with Revision 1.1 and lower, the SD/MMC clock pins are incorrectly labeled. You will notice the name mismatch between the pin-out file and Cyclone V Device Family Pin Connection Guidelines (PDF) . In the Pin Connection Guidelines, the clock pins are named SDMMC_FB_CLK_IN and SDMMC_CCLK_OUT. However, the pin-out file uses the outdated name SDMMC_CLK_IN and SDMMC_CLK. When you cross-reference the pin names from the pin-out file to PCG, relate SDMMC_CLK_IN to SDMMC_FB_CLK_IN and SDMMC_CLK to SDMMC_CCLK_OUT. Resolution . Custom Fields values: ['novalue'] Troubleshooting 2205753649 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] No plan to fix No plan to fix ['Cyclone® V FPGAs and SoCs', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']