Why do I see Unconstrained Output Ports at the EMIF unused pins when compiling the Agilex™ 7 FPGA M-Series EMIF IP? - Why do I see Unconstrained Output Ports at the EMIF unused pins when compiling the Agilex™ 7 FPGA M-Series EMIF IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 or earlier, you may see Unconstrained Output Ports at EMIF unused pins when compiling the Agilex™ 7 FPGA M-Series EMIF IP. Example unconstrained output ports: emif_io96b_<IP Instantiation>_0|emif_io96b_<IP Instantiation>_inst|arch_emif_<string>|wrapper_bufs_mem|g_UNUSED[*].pad Resolution You can safely ignore these unconstrained warnings. This problem is scheduled to be fixed in future releases of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017572457 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']