Why does the Stratix® 10 Avalon® -MM Interface for PCIe* IP with internal DMA send out the read mover "Done" status before it completes the data transfer? - Why does the Stratix® 10 Avalon® -MM Interface for PCIe* IP with internal DMA send out the read mover "Done" status before it completes the data transfer? Description This problem is due to a datapath race condition. The DMA read mover "Done" status update and the completion data are split internally into two (2) different paths/buffers. Data takes a longer path to the Avalon® -MM slave compared to the status update. Resolution This datapath race condition is easily observed in simulation. However, the read mover "Done" status reported a few clock cycles earlier than the data transfer completion will not be a problem in real hardware systems due to latency. Custom Fields values: ['novalue'] Troubleshooting 2205691060 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']