Configurable transceiver enable - Configurable transceiver enable I need to enable transceiver channels in groups based on a board parameter read during board start-up. If the parameter is '0', channels 1 and 2 are enabled, channels 3 and 4 are disabled. If the parameter is '1', channels 3 and 4 are enabled and 1 and 2 are disabled. I want to explicitly disable the unused channels to save power and prevent them from driving outputs. The only way to disable channels that I've figured out is to hold the input reset of the reset controller asserted. Then I'll need 2 reset controllers, one for each group of 2 channels. I'll also need 2 PLLs since they are interconnected with the reset controller. Is this the way to do it or is there a better way? Best regards, Julia Replies: Re: Configurable transceiver enable No worries. I am glad it helped. I will close this case then. Replies: Re: Configurable transceiver enable Sorry, I misunderstood then. My answer was for our custom board-level parameter which defines which channels to activate. Thank you for your reply. I think it answers my question. Replies: Re: Configurable transceiver enable My understanding of " board‑level transceiver parameters are static at power‑up" , implied they are compile‑time only . In practice, changing these parameters would require IP regeneration and a full FPGA recompilation , rather than being something that can be altered dynamically at runtime (i.e., they behave similarly to localparam settings). With that in mind, let me rephrase my understanding of a possible implementation approach: Only 2 channels would be active in normal operation. The remaining channels would be treated as unused channels Only 1 bitstream Based on the transceiver reset architecture described in the Cyclone 10 GX Transceiver PHY User Guide, you may want to consider this conceptual approach to instantiate a 4‑channel transceiver , and control which channel is active using the four independent reset ports per channel : tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset For the unused channels , the handling would be: Assert TX analog reset Assert RX analog reset Keep TX and RX digital reset asserted as well This would prevent the unused channels from calibrating, transmitting, or receiving data, while keeping the configuration static and avoiding any runtime reconfiguration complexity. Replies: Re: Configurable transceiver enable We do not want to maintain two compiled images, then we need to keep track of which board has which image. We want all the boards to have the same image and that they detect their configuration at run-time only. Replies: Re: Configurable transceiver enable How about compiling two separate bitstreams; it would be a clean solution since the board parameter is static at power‑up and there is no requirement to switch channel groups at runtime. Each bitstream instantiates only two transceiver channels, using the Raw (Native) PHY, all operating at the same line rate and reference clock. For each build, the fitter simply needs to be rerun with placement constrained to either channels 1–2 or channels 3–4. Replies: Re: Configurable transceiver enable Hi JonWay, the device is Cyclone 10 GX 10CX105YU484I6G and the transceiver is the 12.5Gbps transceiver. Though I will use it at a lower data rate. The board parameter is static during the entire power-up. The channels operate at the same line rate and have the same reference clock. The channels will be used with a custom protocol, so raw PHYs are instantiated. Best regards, Julia Replies: Re: Configurable transceiver enable Hi Julia, Could you send back the information for the following clarifying questions to make sure the problem is fully understood and to avoid proposing the wrong solution. Which Altera device family and part number are you using, and which transceiver type (e.g., FGT, FHT, GTS)? Is the board parameter static for the entire power‑up , or can it change dynamically after FPGA configuration? Do channels 1–2 and 3–4 operate at the same line rate and reference clock , or do they have different requirements? Are these channels used for a specific protocol (e.g., PCIe, Ethernet, JESD204, Aurora), or are they raw PHYs ? Replies: Re: Configurable transceiver enable .