Why don’t I see the “tx_pmaif_fifo_overflow” port on my RTL instance of the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP when using Intel Quartus Prime Pro Edition Software v22.4? - Why don’t I see the “tx_pmaif_fifo_overflow” port on my RTL instance of the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP when using Intel Quartus Prime Pro Edition Software v22.4? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 22.4, the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP erroneously provides an option to enable the “ Enable tx_pmaif_fifo_overflow port ”. Resolution There is no workaround for this problem. The “ tx_pmaif_fifo_overflow ” port should not be enabled in the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Additional Information This problem has been fixed starting in version 23.1 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18027524368 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']