Error-[ILWOR] Incorrect Logical Worklib or Reflib. The incorrect logical lib is "altera_gpio_core10_ph2_2210". Please check your Synopsys setup file. - Error-[ILWOR] Incorrect Logical Worklib or Reflib. The incorrect logical lib is "altera_gpio_core10_ph2_2210". Please check your Synopsys setup file. Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, you might see this error or a similar one when simulating a subsystem packaged IP, such as EMIF and Nios® IPs. This error occurs when using the simulation scripts generated by the ip-setup-simulation utility. The problem is that the ip-setup-simulation utility does not include the hierarchical information of the internal IPs packaged in the top-level IP in the generated simulation scripts. Resolution To work around this problem, use one of the following methods: Use the quartus_ipgenerate utility: quartus_ipgenerate <project name> [<options>] Use the qsys-generate utility: qsys-generate <.qsys system file to generate> [<options>] Refer to the following command line example for the quartus_ipgenerate utility: quartus_ipgenerate top --simulation=verilog Refer to the following command line example for the qsys-generate utility: qsys-generate top.qsys --quartus-project=top --rev=top --testbench-simulation=verilog Type quartus_ipgenerate -h or qsys-generate -h to see all the available options and the corresponding descriptions. Refer to 7.10. Generate an IP Component or Platform Designer System with quartus_ipgenerate and 7.2.1. qsys-generate Command-Line Options for more information on how to use the quartus_ipgenerate and qsys-generate utilities. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14023866710 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']