What are the definitions of the SPI signals routed from Hard Processor Subsystem (HPS) block to FPGA in Cyclone V SoC and Arria V SoC devices? - What are the definitions of the SPI signals routed from Hard Processor Subsystem (HPS) block to FPGA in Cyclone V SoC and Arria V SoC devices? Description Current documentation does not define all the SPI signals routed from HPS block to the FPGA block within Cyclone ® V SoC and Arria ® V SoC devices. Resolution The description and use of the SPI interface signals is as following. spim0_txd // 1 bit of output data spim0_rxd //1 bit of input data spim0_ss_in_n // In master mode this signal can be used to indicate master contention on the bus. // You can tie it high, i f this function is not used spim0_ss_oe_n // 1 bit of data enable - use it to tri-state the txd bus spim0_ss_0_n // slave select output spim0_ss_1_n // slave select output spim0_ss_2_n // slave select output spim0_ss_3_n // slave select output This information will be updated in a future release of the device handbook. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']