"PLL base data rate" errors in Arria V Transceiver Native PHY IP Core PLL megafunctions - "PLL base data rate" errors in Arria V Transceiver Native PHY IP Core PLL megafunctions Description In the 12.1 Quartus® II software release of the Arria® V Transceiver Native PHY IP Core, the megafunction generated design file displays a default phase-locked loop (PLL) base data rate of 1250 Mbps, regardless of the "PLL base data rate" user configuration in the GUI. Resolution This issue is fixed in the 13.0 Quartus II software release. To workaround this issue in the 12.1 Quartus II software release, change the "Reference Clock Frequency" value in the GUI from the default "125.0 MHz" to any other value at least once before generating the IP core megafunction. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']